Microchip terabit-scale secure ethernet PHY family designed for enterprise, cloud interconnect

文章：Microchip Technology Inc.

需求增加的禁令dwidth and security in network infrastructure driven by growth in hybrid work and geographical distribution of networks is re-defining borderless networking. Led by AI/ML applications, the total port bandwidth for 400G (gigabits per second) and 800G is forecasted to grow at an annual rate of over 50%, according to 650 Group. This dramatic growth is expanding the transition to 112G PAM4 connectivity beyond just cloud data center and telecom service provider switches and routers to enterprise ethernet switching platforms.

Microchip Technology Inc.通过引入一个新的Meta-DX2+ Phys家族，以Meta-DX2以太网PHY（物理层）投资组合对这种市场变化做出反应。These are the industry’s first solution set to integrate 1.6T (terabits per second) of line-rate end-to-end encryption and port aggregation to maintain the most compact footprint in the transition to 112G PAM4 connectivity for enterprise ethernet switches, security appliances, cloud interconnect routers and optical transport systems.

“Introduction of four new META-DX2+ Ethernet PHYs demonstrates our commitment to supporting the industry transition to 112G PAM4 connectivity powered by our META-DX retimer and PHY portfolio. In conjunction with our META-DX2L retimer, we now offer a complete chipset for all connectivity needs from retiming, gearboxing, to advanced PHY functionality,” said Babak Samimi, corporate vice president of Microchip’s communications business unit. “By offering both hardware and software footprint compatibility, our customers can leverage architectural designs across their enterprise, datacenter, and service provider switching and routing systems that can offer pay-as-you-need enablement of advanced features including end-to-end security, multi-rate port aggregation, and precision timestamping via software subscription model.”

META-DX2+’s configurable 1.6T datapath architecture outperforms the next near competitors by 2x in total gearbox capacity and hitless 2:1 protection switch mux modes enabled by its unique ShiftIO capability. The flexible XpandIO port aggregation capabilities optimize router/switch port utilization when supporting low-rate traffic. Also, the devices include IEEE 1588 Class C/D Precision Time Protocol (PTP) support for accurate nanosecond timestamping required for 5G and enterprise business critical services. By offering a portfolio of footprint-compatible retimer and advanced PHYs with encryption options, Microchip enables developers to expand their designs to add MACsec and IPsec based on a common board design and Software Development Kit (SDK).

Key features and capabilities of META-DX2+ include: dual 800 GbE, quad 400 GbE and 16x 100/50/25/10/1 GbE MAC/PHY; integrated 1.6T MACsec/IPsec engines that offload encryption from packet processors so systems can more easily scale up to higher bandwidths with end-to-end security; greater than 20% board savings compared to competing solutions that require two devices to deliver the same 1.6T gearbox and hitless 2:1 mux modes; XpandIO for port aggregation of low-rate Ethernet clients over higher speed Ethernet interfaces, optimized for enterprise platforms; ShiftIO feature combined with a highly configurable integrated crosspoint for flexible connectivity between external switches, processors, and optics; device variants with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes including programmability to optimize power vs. performance; and support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI/ML applications.

650 Group，LLC 650 Group的创始人和技术分析师Alan Weckel表示：“随着行业向112G PAM4串行生态系统的过渡，线路率的加密和端口容量的有效利用变得越来越重要。”“ Microchip的Meta-DX2+家族将在启用MACSEC和IPSEC加密，通过端口聚合优化端口容量，并灵活地将路由/开关硅连接到多速率400G和800G Optics。”

Like the META-DX2L retimer, the new series of META-DX2+ PHYs can be used with Microchip’s PolarFire FPGAs, the ZL30632 high-performance PLL, oscillators, voltage regulators, and other components that have been pre-validated as a system to help speed designs into production.