分阶段阵列PWM DAC

文章：AlperenAkküncü

Several years ago, I wrote an article in Design Ideas called “双µC的PWM频率和分辨率”我提到的地方如何使用两个具有相等值同等循环的PWM信号彼此之间具有相等的占用循环（半个周期延迟）差异。

PWM DAC背后的想法非常简单：它是过滤出PWM信号的所有谐波内容，并仅保留其DC组件。为此，PWM信号是低通滤波的。显然，当您具有较低截止频率的过滤器时，输出将变得更加“无涟漪”，但是瞬态响应将非常慢，反之亦然。

上述文章中提出的想法是生成反相信号，以通过相位取消动作取消某些谐波组件，而不是纯粹依赖滤波器本身。

This idea turned out to be useful in reducing the ripple whilst also improving the transient response. However, its usefulness is kind of limited because not all of the harmonic components of the PWM signals were cancelling each other out. To be more specific, only odd harmonics are cancelling each other and even harmonics are only affected by the filter because when we introduce half a period delay only odd harmonics experiences 180-degree phase shift and even harmonics goes through 360-degree phase shift which is same as being in phase. That results in even harmonics not cancelling each other out.

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实际上，对于50％的占空比（仅包含奇怪的谐波），我们使用此技术获得无纹波输出。对于任何其他占空比，都会有一些连锁反应，但是与单个通道等效相比，连锁幅度仍然会有所改善。我们可以通过使用更多具有不同阶段差异的PWM频道来获得更多无涟漪的职责点来扩展这个想法。

假设我们decided to use n channels at f Hz, if each consecutive PWM channel has 1/(f.n) delay (or 360/n phase shift) with respect to each other then every harmonic components is going to be cancelled because of evenly spaced time delays except for every nth harmonic. To be clearer, let’s say we’re using 10 kHz as our main PWM frequency and we implement four channels with 25µs time delay (90-degree phase shift). In that case, the first channel is our base channel and it doesn’t have delay; the second channel has 25µs delay(90-degree) with respect to the base channel; the third channel has 50µs delay(180-degree) with respect to the base channel; and the last channel has 75µs delay (270-degree) with respect to the base channel.

如前所述，每个连续的通道具有相对于其“相邻”通道的25µs（1/（F.N），F = 10kHz，n = 4）延迟。该电路显示在Figure 1以及一通道和两通道版本。

Figure 1四通道拼手阵列PWM DAC电路以及一频和两通道版本。

此四通道PWM DAC的输出仅包含4个^th基本PWM频率的谐波，因此，当占空比为25％，50％或75％时，输出将不包含连锁反应，因为这些PWM信号没有4^th谐波内容。

在Figures 2,3和4我们可以看到每个电路的输出分别为25％，50％和75％。

Figure 2The circuit with 25% duty cycle.

Figure 3该电路具有50％的占空比。

Figure 4The circuit with 75% duty cycle.

As expected at 25% duty cycle output of the four-channel circuit (dark blue) has almost no ripple and has the fastest transient response; the two-channel circuit (pink) has ripple, but its ripple is less than the single channel’s (light blue) circuit output and it’s faster. At 50% both the two-channel circuit (pink) and four-channel circuit (dark blue) don’t have any ripple, but the four-channel circuit has faster transient response and obviously the single channel (light blue) circuit is slowest and noisiest. And for 75% the results are the same as 25%.

For testing, the circuits are implemented in VHDL using FPGA (GitHub link is shared at the end of the post) because there were many channels and this idea can be further expanded by deploying a lot more channels. Generally speaking, if n channels are implemented, there are going to be n-1 ripple-less duty cycle points (excluding 0% and 100% which are inherently ripple-less). Theoretically, an 8-bit DAC can be implemented using 256 channels with this method, but of course that’s going to be incredibly impractical, but no one can stop you enjoying the idea.

For the sake of completeness, this method is simulated in LTSpice up to eight channels (also in the GitHub link at the end of the post). From the same reasoning, for an eight-channel circuit you should get ripple-free output at multiples of 12.5% duty cycle points; you can see it yourself by downloading the LTSpice file. In the same way if you implement 100 channels you get ripple-less output at every multiple of 1% duty cycle.

总之，通过部署更多具有适当间隔相位延迟的PWM通道，人们可以在某些占空比下实现无连锁反应的输出，即使在随机占用周期下，人们仍然可以提高瞬态响应和噪声性能，这是不可能的，这是不可能的- 通道PWM DAC方法。

GitHub link:https://github.com/alperenakk/pwm_phased_array_dac

This article was originally published onEdn.

Alperen Akküncü是居住在土耳其的电子设计工程师/学生，对精确模拟电路，嵌入式系统和FPGA有兴趣。