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缝合电容器：不完美参考平面的串扰减缓技术

文章：张飞怡

本文讨论了缝合电容器在PCB上分布式飞行中的信号交叉期间引起的缝合串扰的影响。通过3DEM模拟进行了研究，以分析频率和时域的串扰，以及返回路径的表面电流密度。

介绍

在电子系统中，信号传输以近循环形式存在。“正向电流”通过信号轨迹从发射器传播到接收器。相反，“返回电流”从接收器向后行驶，以通过电源或接地平面向发射器右侧发射，该信号迹线右下方用作参考或返回路径。“正向电流”和“返回电流”的路径形成环路电感。将高速信号路由在连续参考平面上是重要的，使得“返回电流”可以在所需路径上传播，直接在信号迹线下方。

When the return path is broken due to the switching of reference planes with different potential, e.g., from ground to power or vice versa after signal crossing over split planes on PCB, the return current might detour and propagate on a longer path, which causes the rise of loop inductance. This might lead to the sharing of common return path by different signals that poses high risk of interference among the signals due to higher mutual inductance. This interference results in signal crosstalk. To mitigate the crosstalk due to imperfect return path, stitching capacitors are mounted on PCB to serve as a bridge between the two reference planes of interest.

3DEM建模信号串扰分析

为了研究缝合电容器在减轻信号串扰中的影响，由于PCB上的信号交叉的信号过度返回路径，3DEM的三个模拟模型使用Keysight EMPRO构建。在模型1A（即，图1中所示的3DEM结构）中，在顶部PCB层上的单端模式下具有50欧姆特征阻抗的两个信号迹线在分割平面上穿过。信号迹线是200密耳长而5米隆宽。同时，层2上的地面和电源平面之间的间隙是20密耳，而实心接地平面在第3层上。所有三个铜层都有1.2密耳。FR4材料用作PCB基板。

两个信号迹线分开15密耳（即，由于“正向电流”传播而导致的最小串扰的信号迹线宽度的Tickple。从串扰角度来看，端口1和端口2终端分别用作侵略者线的发射和接收端。另一方面，端口3和端口4终端用作受害线的发送和接收端。

图1.型号1A中的3DEM结构

In model 1B depicted in Fig. 2, a stitching capacitor is placed across the split planes on the right side (i.e., highlighted in red) to connect electrically the two reference planes on layer 2. The rest of the portion is the same as model 1A. This ideal 0.1uF capacitor, without parasitic resistance (ESR) and parasitic inductance (ESL) serves as a single return path in transmission line.

图2. 1B模型中的3DEM结构

On the other hand, in model 1C depicted in Fig. 3, one more ideal 0.1uF stitching capacitor is placed across the split planes on the left side (i.e., highlighted in red) to connect electrically the two reference planes on layer 2. These two capacitors provide two return paths in transmission line.

图3. 1C模型中的3DEM结构

上述3DEM模型的S41参数或远端串扰（FEXT）在图2中绘制。4（即，跨度从1 MHz到3 GHz）。DB中的绝对值较小的绝对值表示更严重的串扰。With reference to Fig. 4, the most severe signal crosstalk is experienced model 1A (i.e., -32 dB at 500 MHz), followed by 1B (i.e., -36 dB at 500 MHz) and the least severe by 1C (i.e., -41.5 dB at 500 MHz). Model 1A does not have return path at all. Alleviation of crosstalk as much as 10 dB is achieved by providing more return paths using capacitors to bridge the reference planes on layer 2.

FEXT图

图4.模型1A，1B和1C的FEXT图

随后，对上述3种模型进行瞬态仿真，以观察时域中FEXT的现象。In this transient simulation, a square wave signal with 1Gbps data rate (i.e., 500MHz Nyquist frequency), 1.2Vpp amplitude and 5V/ns slew rate is injected into port 1 of each model’s 3DEM model, with port 3 being pulled low (i.e., serves as near end point of victim line), followed by probing at port 4 (i.e., serves as far end point of victim line). Referring to Fig. 5, noise induced at far end point of victim line in time domain for model 1A, 1B and 1C is 135mVpp, 98mVpp and 72mVpp respectively.

The smallest amplitude of noise is induced at far end point of victim line in model 1C due to the least crosstalk incurred, contributed by more return paths provided by the additional stitching capacitor, versus the single return path (i.e., only one stitching capacitor) in model 1B and none return path (i.e., without stitching capacitor at all) in model 1A.

图5.由于串扰，受害者迹线的噪声轨迹的噪声迹象

随后，观察到模式1B与1C通过拼接电容的返回路径上的表面返回电流密度，如图6所示。当在端口1和端口3分别注入500mhz Nyquist频率的方波为同一相位时，正向电流沿最上层PCB层的两条信号道流动，而回流电流从第2层的电源流向接地平面。1B型和1C型通过每个拼接电容的表面返回电流密度分别为60A/m和32A/m。模型1B的电流密度几乎是模型1C的两倍，因为它的单个拼接电容成为两个信号道共用的回路瓶颈，从而增加了互感，从而产生串扰。

模型1

1B型

型号1C.

图6.通过拼接电容为1B（顶部）和1C（底部）的返回路径上的表面电流密度

进一步进行该研究以分析ESR和ESL对减轻串扰引起的影响因子。实际上，离散电容器具有内在的寄生ESR和与其串联的ESL，如图7所示。在上述型号1C上重复3DEM模拟，但分别改变两个缝合电容器中的ESR和ESL的值。参考图1中的FEXT图。如图8所示，0.15OHM的ESR在500MHz附近的频率下将FEXT造成0.03dx。类似地，参考图9中的FEXT图。如图9所示，0.5nh的ESL在500MHz附近的频率下将FEXT加强了1.1dB。ESL至1NH的进一步增加增加了0.35dB至FEXT。