Ensure proper scope setup for correct ESD measurements

Article By : Mike Hertz, Loren Dunn, Mark Maciejka, Dan Steinken

Two of the most common pitfalls in ESD pulse measurement can be avoided when the oscilloscope operator becomes aware of them.

汽车电子组件设计为具有并经过测试以确定对静电放电的一定程度的免疫力(ESD)。测试解决了各种条件,这些条件将遇到的各种条件,包括包装,处理,车辆组装/服务和预期操作。要正确测试任何系统,子系统或IC,您需要测量用于测试DUT的电压波形。不幸的是,典型的示波器设置会产生不正确的结果。您需要知道如何正确触发示波器。另外,您需要从示波器的垂直分辨率中获得最大的收益,以最大程度地提高测试结果。
汽车电磁兼容性(EMC)规格通常在描述测试设置,程序和设备时引用ISO 10605:2008。设备包括一个ESD模拟器,其组件(例如RC网络)产生代表人ESD模型的波形。ISO10605还提供了一种验证ESD模拟器的方法。该方法确保了随着时间的推移以及来自各种制造商的多个实验室和/或ESD模拟器的测试可重复性。正确评估ESD模拟器输出至关重要。
ISO 10605规定了ESD测试级别从2 kV到25 kV in both polarities. Typically, you apply test voltages in steps by increasing the voltage to an established limit. In addition, you must subject component surfaces, interfaces, and electrical terminals to direct air and contact discharges while unpowered, and while configured and operating in a predetermined mode. The component, while powered, may also be exposed to indirect discharges that produce a radiated disturbance. The component needs monitoring for deviations in operation as well as inspected for damage or degradation of performance upon test completion. Similar procedures are also performed to the full vehicle.
ESD模拟器的验证包括表征放电脉冲波形。ISO 10605的第二版标识了上升时间,第一峰值电流,电流在T1和T2处的电流为感兴趣的参数(figure 1). The values of t1and t2vary with the value of R and C in a given RC network for the purpose of verifying its time constant.

[EDNAOL 2016JUN24 TA 01FIG1] *图1:Measurement parameters of interest include rise time, first peak current, current at t1,最新2在ESD脉冲上。*

图2shows an ESD simulator gun applying a contact discharge into a current shunt target that is connected to the oscilloscope's 50 Ω DC coupled input through a double shielded cable and inline attenuators.

[EDNAOL 2016JUN24 TA 01FIG2] *图2:An ESD gun discharges into a current shunt target. The resulting pulse waveform is captured and measured with an oscilloscope.*

Although this measurement is a standard requirement, it's often inaccurately performed because of the oscilloscope's threshold setting and vertical sensitivity. Traditional pulse measurements require an oscilloscope to find the steady-state high and low values of the pulse and then compute pulse parameters such as rise time based on these steady state levels. A problem occurs when using industry default measurement thresholds.
The red histogram infigure 3识别波形的顶部和底座。对于时钟信号,默认阈值会自动识别波形的0%和100%级别,并且为时钟波形正确计算了诸如上升时间之类的时序测量值。

[Ednaol 2016Jun24 TA 01Fig3] *Figure 3:Default oscilloscope measurement parameters incorporate the IEEE clock pulse definitions, which use the top and base of a waveform. These values correctly identify thresholds for clock pulses, but will incorrectly define the 0% and 100% levels of an ESD pulse.
*
但是,当应用于ESD脉冲时,这种阈值放置方法是不正确的。在这种情况下,标准的IEEE顶部和基本阈值会误导标记为“顶部”的半稳定部分的100%阈值figure 4and will also misidentify the 0% threshold as the prolonged decay area labelled "base" rather than using the Zero Volt and Maximum ESD pulse values required in standards IEC 61000-4-2 and ISO 10605. Because these standards require that the 100% threshold to be placed at the Maximum level of the waveform, and the 0% threshold to be placed at the Zero Volts level, default threshold placement will result in an erroneous rise time calculation of an ESD pulse.

[Ednaol 2016Jun24 TA 01Fig4] *Figure 4:Default oscilloscope measurement thresholds incorrectly identify the Top and Base of an ESD pulse using IEEE clock pulse definitions, resulting in ESD measurement errors.*

Oscilloscopes will, by default, misinterpret the prolonged decay area of the pulse, highlighted with a dashed red line infigure 5, as being the 100% steady-state Top level of the waveform (and the peak of the waveform misidentified as being overshoot). Using default thresholds, the oscilloscope will incorrectly calculate the pulse's rise time. Considering the vertical distance between the dashed red line and the solid green line offigure 5, is it easy to envision how the rise time could be miscalculated with an error margin between 100% and 800% error, relative to EMC standard specification requirements. A critical step to prevent this measurement error from happening is to configure the automatic thresholds to instead be the Zero Volt level and the waveform Maximum level, as shown circled in green.
[Ednaol 2016Jun24 TA 01Fig5] *Figure 5:所需的ESD脉冲阈值是用绿线识别的,默认阈值在此获得的ESD脉冲上用虚线的红线说明。

Maximise dynamic range
The second most common source of inaccuracy in ESD pulse measurements is the selection of volts per division.图6shows how an oscilloscope first amplifies the analogue input signal (in this case an ESD pulse) in the analogue amplifier stage and then outputs the signal to the ADC (analogue-to-digital converter). The oscilloscope's dynamic range is determined by the range of signal amplitudes that the ADC can process effectively. The minimum of the range occurs where signal power equals noise power. The maximum of the range occurs at or near full scale where maximum counts of the ADC are used while digitizing the waveform and distortion is minimised.

[EDNAOL 2016JUN24 TA 01Fig6] *图6:ESD脉冲需要占据示波器放大器阶段的大部分垂直范围,以最大化动态范围。

If an ESD pulse is acquired while occupying only half of the vertical scale of the screen, then the acquired waveform will lose one bit of resolution (and half of its dynamic range) impacting both vertical and horizontal measurements on the waveform. Horizontal measurements are directly impacted by timing uncertainty at measurement points from spurious noise.
许多示波器用户并不知道,对于所有可用的数字化示波器,显示屏幕上获得的波形的垂直分辨率与波形垂直捕获的屏幕百分比成正比。
图7显示了ESD脉冲获得的全尺度,垂直占据了完整的网格。此采集可最大程度地减少定量噪声。因为获得的波形的定量噪声会影响垂直和水平测量精度(因此影响诸如上升时间之类的测量值),因此获得的ESD脉冲的缩放是必不可少的

[EDNAOL 2016JUN24 TA 01Fig7] *图7:The ESD pulse needs to occupy most of the vertical range of an oscilloscope's amplifier stage to maximise dynamic range.*

图8在仅占用网格垂直空间的一半时,显示出相同的ESD脉冲。EMC实验室中的典型台式示波器示波器包含8位ADC硬件,其中有2个8= 256 quantisation levels. When only half of the vertical range of the display grid is utilised, this results in only half of the ADC range used when the signal is supplied from the analogue amplifier output stage (recallfigure 5),ADC范围的另一半没有任何收益。因此,仅使用128个定量水平,导致128 = 27=获得的ESD脉冲上的7位分辨率。

[EDNAOL 2016JUN24 TA 01Fig8] *图8:An ESD pulse occupying half of the vertical range of the grid loses one effective bit during acquisition, resulting in loss of vertical and horizontal measurement accuracy.*

图9显示了相同的ESD脉冲获得脉冲occupies only one quarter of the display grid, resulting in only ¼ of the dynamic range of the oscilloscope being applied to the signal. When using one-fourth of the dynamic range, which uses just 64 of the 256 quantisation levels to acquire the ESD pulse, or 64 = 26= 6bit resolution on the acquired ESD pulse. The loss of vertical resolution results in increased quantisation noise impacting both vertical and timing measurements, which can have a critical effect on ESD pulse rise time measurements. That's based simple on the operator's selection of V/div setting used during acquisition.

[EDNAOL 2016JUN24 TA 01Fig9] *图9:An ESD pulse occupying one quarter of the vertical range of the grid loses three quarters of the ADC range and loss of two effective bits during acquisition, resulting in significant quantisation and measurement error.*

For this reason, vertical scaling of any digitizing oscilloscope should be set to maximise the ESD pulse shape vertically within the display grid as shown in Figure 7. This often overlooked step has a profound impact on signal integrity and ESD pulse measurement results.
Note that for RC networks where R=2 kΩ, the ratio of the first peak current to the current at t2is 25:1. This is the largest ratio of measured amplitudes in a single waveform capture during verification and provides a great case for taking full advantage of an oscilloscope's dynamic range.
In summary, two of the most common pitfalls in ESD pulse measurement can be avoided when the oscilloscope operator becomes aware of them. The default threshold measurements of Top and Base must be changed to 0 V – Max to avoid incorrect automatic threshold placement, and the vertical scaling of the ESD pulse used during verification should fill most of the grid vertically in order to maximise dynamic range and signal integrity.

关于作者
Mike Hertz is a field applications engineer at Teledyne LeCroy.
Loren Dunn is manager of the Hitachi Automotive Systems test laboratories in Farmington Hills, Mich.
Mark Maciejka is a lead engineer at the Hitachi Automotive Systems EMC test laboratory..
Dan Steinken is a sales engineer with Teledyne LeCroy.

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